Mismatch-Immune Successive-Approximation Techniques for Nanometer CMOS ADCs

[摘要] During the past decade, SAR ADCs have enjoyed increasing prominence due to theirinherently scaling-friendly architecture. Several recent SAR ADC innovations focus on decreasing power consumption, mitigating thermal noise, and improving bandwidth, howevermost of those that use non-hybrid architectures are limited to moderate (8-10 bit) resolu-tion. Assuming an almost rail-to-rail dynamic range, comparator noise and DAC elementmismatch constraints are critical but not insurmountable at 10 bits of resolution or less insub-100nm processes. On the other hand, analysis shows that for medium-resolution ADCs(11-15 bits, depending on the LSB voltage of the converter), the mismatch sizing constraintstill dominates unit capacitor sizing over the kT/C sampling noise constraint, and can only be mitigated by drawing increasingly larger capacitors.The focus of this work is to extend the scaling benefits of the SAR architecture to mediumand higher ADC resolutions through mitigating and ultimately harnessing DAC element mismatch. This goal is achieved via a novel, completely reconfigurable capacitor DAC that allows the rearranging of capacitors to different trial groupings in the SAR cycle so that mismatch can be canceled. The DAC is implemented in a 12-bit SAR ADC in 65nm CMOS, and a nearly 2-bit improvement in linearity is demonstrated with a simple reconfiguration algorithm.

[发布机构] University of Michigan

[效力级别] Mismatch in Successive Approximation Analog-to-Digital Converters

[关键词] Mismatch in SAR ADCs;Mismatch in Successive Approximation Analog-to-Digital Converters;Electrical Engineering;Engineering;Electrical Engineering