Parameter extraction of superconducting integrated circuits

[摘要] Integrated circuits are expensive to manufacture and it is important to verify the correctoperation of a circuit before fabrication. Efficient, though accurate, parameter extractionof post-layout designs are required for estimation of circuit success rates. This thesisdiscusses electrical netlist and fast parameter extraction techniques suited for both intraandinter-gate connections. This includes the use of extraction windows and look-up tables(LUTs) for accurate inductance and capacitance estimation. These techniques can readilybe implemented in automated layout software where fast parameter extraction is requiredfor timing analysis and gate placement.

[发布机构] Stellenbosch University