An ultra low power and low complexity all digital PLL with a high resolution digitally controlled oscillator

[摘要] References(7)In this letter, a new all digital phase locked loop (ADPLL) is proposed. The proposed ADPLL is introduced a new locking procedure with low complexity which results in an ultra low power design. The design uses only two up-down counters for finding the reference frequency. An efficient glitch removal filter and a new low power DCO are also introduced in this letter. The DCO achieves a reasonably high resolution of 1ps. The power consumption of the proposed ADPLL at 500MHz frequency is 820µW. The proposed ADPLL is simulated in 180nm CMOS with Hspice and verified by MATLAB.

[学科分类] 电子、光学、磁材料

[关键词] all digital phase locked-loop;digitally controlled oscillator;glitch removal;low power;low complexity