A wide-range all-digital duty-cycle corrector with output clock phase alignment in 65nm CMOS technology

[摘要] References(10)A wide-range all-digital duty-cycle corrector (ADDCC) with output clock phase alignment is presented in this paper. The proposed ADDCC can correct the duty-cycle error of the input clock to 50% duty-cycle. The acceptable duty-cycle range and frequency range of input clock is from 20% to 80% and from 250MHz to 1GHz, respectively. The proposed ADDCC is implemented on a standard performance 65nm CMOS process, and the power consumption is 1.52mW at 250MHz and 5.83mW at 1GHz, respectively.

[学科分类] 电子、光学、磁材料

[关键词] clocks;delay lines;duty cycle corrector