Optimization of CMOS power-cell layout for improving junction breakdown

[摘要] References(9)Complementary metal-oxide-semiconductor (CMOS) power cells for power amplifiers (PAs) were implemented and measured using a standard 0.35-µm CMOS process. An experimental analysis on the effect of substrate resistance on junction breakdown voltage is carried out to optimize the power-cell layout for CMOS PA applications. An optimized power-cell layout for improving junction breakdown voltage is proposed and verified through experiments in this work.

[学科分类] 电子、光学、磁材料

[关键词] CMOS;power cell;substrate resistance;junction breakdown;gate finger;gate finger width