Multiple nodes upset tolerance DICE latch based on on-state transistor

[摘要] References(15)Cited-By(3)A reliable single-event upset (SEU) hardened latch is proposed to enhance the multiple nodes upset tolerance. By using the on-state transistor, half of the sensitive transistor pairs can be reduced compared to the typical DICE latch. Technology computer-aided design (TCAD) simulation is used to verify the hardening performance of our proposed latch.

[学科分类] 电子、光学、磁材料

[关键词] multiple nodes;DICE;on-state transistor;SEU