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Design methodology for determining the number of stages in a cascaded time amplifier to minimize area consumption
[摘要] References(4)Cited-By(2)This paper describes a design methodology for determining the number of stages in a cascaded time amplifier to minimize the area consumption. The total area consumption is categorized into three parts, which allows mathematical analysis and optimization to be performed. A combination of the proposed mathematical analysis and 2D mapping can determine the number of stages to minimize the area consumption.
[发布日期]  [发布机构] 
[效力级别]  [学科分类] 电子、光学、磁材料
[关键词] time amplifier;CMOS;integrated circuits;design methodology;design for testability [时效性] 
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