Power modeling for digital circuits with clock gating

[摘要] References(12)Cited-By(1)A power model for digital circuits with clock gating is proposed. The power states are defined by the values of clock gating enable signals. The power consumption for each power state is characterized by the low-level power analysis results. Experimental results show that the proposed power model achieves about 400 times faster analysis speed with less than 1% of error on average comparing to gate-level power models.

[学科分类] 电子、光学、磁材料

[关键词] power model;clock gating;high-level;power analysis