Wide frequency range duty cycle correction circuit for DDR interface

[摘要] References(6)Cited-By(1)The proposed wide-range digital duty cycle correction (DCC) circuit corrects an arbitrary input clock duty ratio to 50% while preserving the output clock phase even when the input clock duty ratio suddenly changes. Also, DCC control information is preserved during power-down mode. In this work, for input frequency range of 500MHz to 2GHz with ±10% duty ratio error, the output duty ratio error is corrected to be less than ±1.4%. The proposed DCC circuit is designed and verified using a 0.18um CMOS technology.

[学科分类] 电子、光学、磁材料

[关键词] duty cycle correction;duty detector;double date rate