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An improved reverse converter for the moduli set {2n-1, 2n, 2n+1, 2n+1-1}
[摘要] References(6)Cited-By(12)In this paper, a new reverse converter for the moduli set {2n-1, 2n, 2n+1, 2n+1-1} is presented. We improved a previously introduced reverse converter architecture for deriving a high-speed hardware design. Hardware architecture of the proposed converter is based on adders, without the need for ROM or Multiplier. The presented design resulted in a significant reduction in conversion delay in comparison to the last reverse converter for the moduli set {2n-1, 2n, 2n+1, 2n+1-1}.
[发布日期]  [发布机构] 
[效力级别]  [学科分类] 电子、光学、磁材料
[关键词] residue number system;reverse converter;VLSI architectures [时效性] 
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