A highly digital, reconfigurable and voltage scalable SAR ADC

[摘要] (cont.) Power gating of the digital logic is used to reduce leakage power at low sample rates. Reconfigurability between single-ended or differential modes enables a power versus performance trade-off. Lastly, programmable sampling duration and internal bootstrapping is used to maintain sampling linearity at low voltages. The ADC has been submitted for fabrication in a low power 65nm digital CMOS process and simulation results are presented.

[发布机构] Massachusetts Institute of Technology