PVT variation-aware timing analysis and adaptive circuit techniques for robust synchronous integrated circuits

[摘要] Over the last few years, considerable variability in deep submicron integrated circuits has become a major concern for designers since the actual performance can vary drastically from the predicted performance leading to yield loss. Potential solutions and research trends include better estimation of the variability impact to reduce circuit overdesign, and adaptable and redundant circuits which provide inherent circuit robustness to variability. In this thesis, we develop accurate models for PVT induced delay variability as well as self-adjusting adaptive circuits that alleviate many of the present and future problems associated with variability. We present a new model that approximates the BSIM4 MOSFET equations to derive the resistances of the pull-up and pull-down networks and thereby derive the noise rejection curves without performing expensive circuit simulations. The model can predict the effect of parameter variations on the noise rejection curves accurately since it is based upon device equations. Our model can predict the noise susceptibility under parameter variations more than five orders of magnitude faster than circuit simulations, which makes it suitable for design optimization for noise robustness. Furthermore, we present a thermally adaptive 3D clocking scheme that senses the ambient temperature and dynamically adjusts the driving strengths of the clock buffers to reduce the clock skew between terminals. Simulation results demonstrate that the dynamically adaptive design technique is capable of reducing the clock skew, leading to thermally robust clock tree designs for 3D integrated circuits. Additionally, we present an adaptive clock buffer circuit design and an adaptive clock distribution network to mitigate the effect of global power-supply variations on clock distribution buffers as well as local variations on local pipelined logic circuits. The adaptive buffer provides a supply insensitive propagation delay to minimize the clock skew in clock distribution networks, as well as dynamic clock skew scheduling to prevent timing violations. We present another adaptive circuit design that is capable of increasing the effective size-ratio for extended balanced operation in the subthreshold region as well as decreasing the size-ratio for high performance at the nominal V DD . Therefore, for designs working under DVS schemes, our technique presents a suitable solution for balanced minimum energy operation.

[发布机构] Rice University

[效力级别] engineering