ASPEN: High-performance hardware support for distributed shared-memory

[摘要] This thesis describes and evaluates an integrated memory and network subsystem designed to provide the abstraction of shared memory among workstations. The work is embodied in Aspen$spdag$, the integrated memory and network communication system developed for the purpose of evaluating our design decisions.Aspen combines a mesh of rings with snooping hardware to provide full and localized broadcasting capability. Its coherence mechanism uses an update-with-timeout protocol, a hybrid between pure invalidation and update protocols. A relaxed memory consistency model allows the buffering of writes to memory. Routing of messages is accomplished with a novel distributed-directory scheme. Synchronization is provided by the hardware in the form of lock and barrier support. Dual ported memory at the network interface reduces contention between the bus and the network for the large secondary cache.In order to evaluate Aspen, we implemented a cycle-level simulator capable of emulating a variety of architectural configurations. Simulation parameters included the second-level cache line size, the memory consistency model, and the update time-out setting. Using this simulator, we compared Aspen to other approaches to the problem of shared memory computing. In a simulated 64-processor system, Aspen exhibited application speedups ranging from 37 to 61, depending upon the application. We present additional experimental data that suggests Aspen is scalable to larger numbers of processors with comparable performance. ftn$spdag$A grove of Aspen trees, while appearing to be a collection of individuals, is actually a single organism with a common root system.

[发布机构] Rice University

[效力级别] science