Implementation and performance evaluation of a fast relocation method in a GPS/SINS/CSAC integrated navigation system hardware prototype

[摘要] In this paper, a fast relocation method is proposed, implemented and evaluated in a DSP/FPGA based GPS/SINS/CSAC deep integration hardware prototype. For the GPS receiver, when signal appears after the signal blockage or signal interference, the precise time information based on the reference of the CSAC and the position information from the SINS combined with the ephemeris can be used to calculate the frame counts and aid the realization of the fast relocation. A field test is conducted to verify and evaluate the performance of the algorithm. The results demonstrate that the proposed fast relocation algorithm can largely reduce the receiver relocation time. The result shows the relocation can be realized during 1 second while the traditional receiver usually needs at least 6 seconds for the relocation after the signal blockage.

[学科分类] 电子、光学、磁材料

[关键词] chip scale atomic clock;deep integration;fast relocation;signal blockage;field test