A novel obstacle-aware multiple fan-out symmetrical clock tree synthesis

[摘要] Clock tree design plays a critical role in improving chip performance and affecting power. In this paper, we propose a novel symmetrical clock tree synthesis algorithm, including tree architecture planning, matching, merging, embedding and buffer insertion. Obstacle-aware placement and routing are also integrated into the algorithm flow. By using NGSPICE simulation for benchmark circuits, our skew results decrease by 17.2% while using less than 24.5% capacitance resource compared with traditional symmetrical clock tree. Further, we also validated the algorithm in ASIC design.

[学科分类] 电子、光学、磁材料

[关键词] symmetrical clock tree;multiple fan-out;matching algorithm;buffer insertion;obstacle-aware placement and routing