Design of hardware accelerator for Lempel-Ziv 4 (LZ4) compression

[摘要] Hardware accelerators are being considered as important architectural components in the context of datacenter customization to achieve high performance and low power. Compression has played an important role in computer systems by enhancing storage and communication efficiency in the charge of extra computational cost. In this letter, we present a fully pipelined compression accelerator for the Lempel-Ziv (LZ) compression algorithm. The compression accelerator is verified by using FPGA and fabricated using 65 nm CMOS technology.

[学科分类] 电子、光学、磁材料

[关键词] data compression;LZ4;hardware accelerator;high throughput