A 2.4-GHz all-digital phase-locked loop with a pipeline-ΔΣ time-to-digital converter

[摘要] A 2.4-GHz all-digital phase-locked loop (ADPLL) for Zigbee application is presented. The proposed pipeline-ΔΣ TDC is based on two-stage time quantization with pulse-train time amplifiers. It achieves an SNDR of 80 dB and a high resolution up to 0.23 ps. A MASH 1-1-1 ΔΣ modulator based on vernier lines is used to achieve third-order noise shaping. The proposed ADPLL has been implemented in a 0.13-µm CMOS technology. The measurement results show a 12-mW total power consumption. The in-band and out-band phase noise are −91 dBc/Hz@10 kHz and −128 dBc/Hz@1 MHz, respectively. The RMS jitter and peak-peak jitter are 2.9 ps and 21.5 ps, respectively.

[学科分类] 电子、光学、磁材料

[关键词] Î”Σ-TDC;pipeline;noise shaping;ADPLL