Low Energy Solutions for FIFOs in Networks on Chip

[摘要] To continue the progress of Moore's law at the end of Dennard Scaling, computer architects turned to multi-core systems, connected by networks-on-chip (NoCs). As this trend persisted, NoCs became a leading energy consumer in modern multi-core processors, with a significant percent originating from the large number of virtual channel (FIFO) buffers. In this work, two orthogonal methods to reduce the use-phase energy of these FIFO buffers are discussed. The first is a reservation based circuit-switching multi-hop routing design, multi-hop segmented circuit switching (MSCS). In a 2D arrangement of an NoC, MSCS performs network control at most once in each dimension for a packet, compared to leading multi-hop approaches which often require multiple arbitration steps. This design resulted in a reduction of FIFO buffer storage by 50% over the leading multi-hop scheme with a nominal latency improvement (1.4%). The second method discussed is the intelligent replacement of SRAM with Domain-Wall Memory (DWM) FIFOs, enabled by novel control schemes which leverage the ''shift-register'' nature of spintronic DWM to create extremely low-energy FIFO queues. The most efficiently designed shift-based buffer used a dual-nanowire approach to more effectively align read and writes to the FIFO with the limited access ports.

[发布机构] the University of Pittsburgh