The bias-stress effect in pentacene organic thin-film transistors

[摘要] (cont.) This behavior of [delta]V saturation despite the presence of free carriers in the channel is observed for the first time in a TFT. Through the temperature measurements, we identify that the source of the long time constants for trapping is the high energy barriers for carriers to be trapped. The effective energy barrier is found to be 0.8 eV for the measured pentacene OTFTs. The time constants associated with the traps are dispersed due to the disorder in the pentacene and gate dielectric. The dependencies of the BSE to various stress conditions are modeled, which allows prediction of [delta]V for different stress times and voltages. The model is used to estimate the implication of the BSE on circuit applications and usable lifetime. Full recovery of the original I-V characteristics occur when the bias stress is removed. The recovery is found to have time dependency and thermal activation energy that is similar to the BSE implying that the recovery mechanism is similar to that of the BSE. The application of the negative VSG accelerates recovery, which serves as evidence that the recovery is achieved by detrapping of the trapped carrier. Possible mechanisms for the BSE and its recovery are discussed based on the experimental observations. A new annealing process which improves mobility, contact resistance, and operational stability has been developed. Experimentally the annealing process increased mobility from 0.03 to 0.05 cm2/Vs and decreased contact resistance from 185 to 38 K[ohm]-cm. The overall improvement in stability is over eight times for a wide range of stress conditions. The stability is found to be increased by the reduction of the trap density and the decrease of the trapping rate.

[发布机构] Massachusetts Institute of Technology