Delay locked loop integrated circuit.
[摘要] This report gives a description of the development of a Delay Locked Loop (DLL) integrated circuit (IC). The DLL was developed and tested as a stand-alone IC test chip to be integrated into a larger application specific integrated circuit (ASIC), the Quadrature Digital Waveform Synthesizer (QDWS). The purpose of the DLL is to provide a digitally programmable delay to enable synchronization between an internal system clock and external peripherals with unknown clock skew. The DLL was designed and fabricated in the IBM 8RF process, a 0.13 {micro}m CMOS process. It was designed to operate with a 300MHz clock and has been tested up to 500MHz.
[发布日期] 2007-10-01 [发布机构]
[效力级别] [学科分类] 工程和技术（综合）
[关键词] INTEGRATED CIRCUITS;DESIGN;FABRICATION;SYNCHRONIZATION;WAVE FORMS Digital integrated circuits-Design and construction.;Integrated circuits. [时效性]
