Fine Control of Local Whitespace in Placement

[摘要] In modern design methodologies, a large fraction of chip area during placement is left unused by standard cells andallocated as “whitespace." This is done for a variety of reasonsincluding the need for subsequent buffer insertion, as a means toensure routability, signal integrity, and low coupling capacitancebetween wires, and to improve yield through DFM optimizations.To this end, layout constraints often require a certain minimumfraction of whitespace in each region of the chip. Our workintroduces several techniques for allocation of whitespace inglobal, detail, and incremental placement. Our experiments showhow to efficiently improve wirelength by reallocating whitespacein legal placements at the large scale. Additionally, for thefirst time in the literature, we empirically demonstrate high-precisioncontrol of whitespace in designs with macros andobstacles. Our techniques consistently improve the quality ofwhitespace allocation of top-down as well as analytical placementmethods and achieve low penalties on designs from the ISPD 2006placement contest with minimal interconnect increase.

[学科分类] 电子、光学、磁材料