A low power clock generator with adaptive inter-phase charge balancing for variability compensation in 40-nm CMOS

[摘要] Power dissipation besides chip area is still one main optimization issuein high performance CMOS design. Regarding high throughput building blocksfor digital signal processing architectureswhich are optimized down to the physicallevel a complementary two-phase clocking scheme (CTPC) is oftenadvantageous concerning ATE-efficiency.The clocksystem dissipates a significant part of overall power up to more than 50%in some applications.

One efficient power saving strategy forCTPC signal generation is the charge balancing technique.To achieve high efficiency with this approacha careful optimization of timing relations within the controlisinevitable.

However, as in modern CMOS processes device variationsincrease,timing relations betweensensitive control signalscan be affected seriously.In order to compensate for the influence of global and local variations in thiswork, an adaptive control system for charge balancing in a CTPC generatoris presented. An adjustment for the degree of charge recycling is performedin each clock cycle.In the case of insufficient recyclingthe delay elements which define duration and timing position ofthe recycling pulse are corrected by switchable timing units.

In a benchmark with the conventional clock generation system,a power reduction gainof up to 24.7% could be achieved. This means saving in powerof more than 12% for a complete number-crunching building block.

[学科分类] 电子、光学、磁材料