Quantitative design space exploration of routing-switches for Network-on-Chip

[摘要] Future Systems-on-Chip (SoC) will consist of many embedded functional unitslike e.g. embedded processor cores, memories or FPGA like structures. TheseSoCs will have huge communication demands, which can not be fulfilled bybus-based communication systems. Possible solutions to this problem are socalled Networks-on-Chip (NoC).

These NoCs basically consist of network-interfaces which integratefunctional units into the NoC and routing-switches which connect thenetwork-interfaces. Here, VLSI-based routing-switch implementations arepresented. The characteristics of these NoCs like performance and costs(e.g. silicon area respectively logic elements, power dissipation) depend ona variety of parameters. As a routing-switch is a key component of a NoC,the costs and performance of routing-switches are compared for differentparameter combinations. Evaluated parameters are for example data wordlength, architecture of the routing-switch (parallel vs. centralizedimplementation) and routing-algorithm.

The performance and costs of routing-switches were evaluated using anFPGA-based NoC-emulator. In addition different routing-switches wereimplemented using a 90 nm standard-cell library to determine the maximumclock frequency, power-dissipation and area of a VLSI-implementation. Thepower consumption was determined by simulating the extracted layout of therouting-switches. Finally, these results are benchmarked to otherrouting-switch implementations like Aetheral and xpipes.

[学科分类] 电子、光学、磁材料