A low latency semi-systolic multiplier over GF(2m)

[摘要] References(8)Cited-By(1)A finite field multiplier is commonly used in implementations of cryptosystems and error correcting codes. In this paper, we present a low latency semi-systolic multiplier over GF(2m). We propose a finite field multiplication algorithm to reduce latency based on parallel computation. The proposed multiplier saves at least 31% time complexity as compared to the corresponding existing structures.

[学科分类] 电子、光学、磁材料

[关键词] cryptography;finite field arithmetic;modular multiplication;semi-systolic array